Name
Title | ||
|---|---|---|
Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology |
Abstract | ||
|---|---|---|
This paper describes different solutions to decrease dynamic consumption of circuits processed on an embedded non-volatile memories CMOS 80 nm technology. Up to 25 % in dynamic power reduction is demonstrated without degrading performances and static leakages of devices and above all, with full DMR compliancy. Ring oscillator designs are used to estimate the dynamic power gain, comparing new development process (B) to reference process (A) currently in use in manufacturing. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/MWSCAS.2014.6908560 | Circuits and Systems |
Keywords | Field | DocType |
CMOS memory circuits,oscillators,random-access storage,CMOS embedded nonvolatile memory technology,design optimization,development process,device static leakages,dynamic power gain estimation,dynamic power reduction,full-DMR compliancy,process optimization,reference process,ring oscillator design,size 80 nm,CMOS inverter,Low power,carriers mobility enhancement,dynamic/static power,ring oscillator,standard cell | Computer science,CMOS,Electronic engineering,Dynamic demand,Embedded system | Conference |
ISSN | Citations | PageRank |
1548-3746 | 1 | 0.48 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Innocenti, J. | 1 | 1 | 0.48 |
| Welter, L. | 2 | 1 | 0.48 |
| Julien, F. | 3 | 1 | 0.48 |
| Lopez, L. | 4 | 2 | 1.11 |