Name
Abstract | ||
|---|---|---|
Interconnect opens are known to be one of the predominant defects in nanoscale technologies. However, automatic test pattern generation for open faults is challenging, because of their rather unstable behaviour and the numerous electric parameters which need to be considered. Thus, most approaches try to avoid accurate modeling of all constraints and use simplified fault models in order to detect as many faults as possible or make assumptions which decrease both complexity and accuracy. This paper presents a new SMT-based approach which for the first time supports the Robust Enhanced Aggressor Victim model without restrictions and handles oscillations. It is combined with the first open fault simulator fully supporting the Robust Enhanced Aggressor Victim model and thereby accurately considering unknown values. Experimental results show the high efficiency of the new method outperforming previous approaches by up to two orders of magnitude. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.7873/DATE.2014.138 | Design, Automation and Test in Europe Conference and Exhibition |
Keywords | Field | DocType |
automatic test pattern generation,integrated circuit interconnections,integrated circuit testing,nanoelectronics,SAT modulo theory,SMT-based ATPG,automatic test pattern generation,interconnect open defects,nanoscale technologies,robust enhanced aggressor victim model,ATPG,Interconnect opens,SMT,test generation,unknown values | Nanoelectronics,Automatic test pattern generation,Computer science,Real-time computing,Electronic engineering,Fault Simulator,Interconnection,Order of magnitude | Conference |
ISSN | Citations | PageRank |
1530-1591 | 9 | 0.50 |
References | Authors | |
24 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dominik Erb | 1 | 9 | 0.50 |
| Karsten Scheibler | 2 | 9 | 0.50 |
| Matthias Sauer | 3 | 9 | 0.84 |
| Bernd Becker | 4 | 9 | 0.50 |