Paper Info
Title
Low-power design methodology for CML and ECL circuits
Abstract
This paper presents a design methodology to enable the design of power efficient, high-speed CML/ECL circuits. It covers library requirements as well as proposed architectural improvements for power optimization. At transistor level, a voltage supply reduction from 3.3V to 2.5V is enabled by modifying classical three-level stack CML latch topology. Secondly, implementing several speed classes using different load resistor variants of most important gates allows for more efficient balancing of critical paths. The methodology is exemplary demonstrated on an 4:1 Serializer with 2 times 2×4 bit FIFO designed in low-cost 0.25 μm SiGe BiCMOS process. AMS schematic simulation results show that both approaches lead to a reduction of the overall current of 39% to 58.68 mA, resulting in a total power dissipation of 146.70mW. The maximal data rate of 12.5 Gb/s is achieved, whereas 54% of the total power could be saved compared to baseline 3.3V design.
Year
DOI
Venue
2014
10.1109/PATMOS.2014.6951898
Power and Timing Modeling, Optimization and Simulation
Keywords
Field
DocType
BiCMOS integrated circuits,Ge-Si alloys,current-mode logic,emitter-coupled logic,low-power electronics,semiconductor materials,4:1 Serializer,AMS schematic simulation,BiCMOS process,ECL circuits,FIFO,SiGe,classical three-level stack CML latch topology,low-power design methodology,power dissipation,power optimization,size 0.25 mum,voltage 3.3 V to 2.5 V,voltage supply reduction,CML,Current Mode Logic,Design Methodology,ECL,Emitter Coupled Logic,Low Power
Logic gate,Power optimization,Pass transistor logic,Computer science,Real-time computing,Serializer,Electronic engineering,Schematic,Resistor,Transistor,Electronic circuit
Conference
Citations 
PageRank 
References 
2
0.40
3
Authors
4
Name
Order
Citations
PageRank
Oliver Schrape1199.55
Markus Appel241.26
Frank Winkler3369.50
Milos Krstic417039.42