Name
Abstract | ||
|---|---|---|
High Efficiency Video Coding (HEVC) standard achieves enhanced compression efficiency in comparison to previous standards, at the cost of a dramatic increase of the computational load. In order to cope with such computational requirements, and to challenge the real-time encoding of High Definition (HD) video sequences with the HEVC standard, we propose herein a reconfigurable architecture design for the most computationally demanding motion estimation module, considering highly efficient Full-Search Block-Matching algorithm. The proposed architecture supports Prediction Blocks (PBs) sizes ranging from 8×8 to 64×64 pixels (also considering non-square shapes), and search areas as large as 256×256 pixels. Furthermore, this reconfigurable approach leverages the trade-off between maximum performance and minimum resource usage. Experimental results show that the proposed architecture is able of achieving real-time motion estimation with more than 26.9 fps, for 1080p video formats, a 64×64 pixels search area and 1 reference frame, by relying on a Xilinx Virtex 5 FPGA implementation. Moreover, a performance superior to the NVIDIA Fermi-based GPU implementation, for up to 25%, was achieved. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ICIP.2014.7025244 | Image Processing |
Keywords | Field | DocType |
data compression,field programmable gate arrays,graphics processing units,image matching,image sequences,motion estimation,video coding,HD video sequences,HEVC motion estimation,HEVC standard,NVIDIA Fermi-based GPU implementation,PB,Xilinx Virtex 5 FPGA implementation,compression efficiency,full-search block-matching algorithm,high definition video sequences,high efficiency video coding standard,prediction blocks,reconfigurable architecture design,reconfigurable data flow engine,FPGA,Full-Search Block-Matching,HEVC,Maxeler,Motion Estimation,Variable Block-Size | Reference frame,Quarter-pixel motion,Computer science,Real-time computing,Artificial intelligence,Virtex,Motion estimation,Computer engineering,Computer vision,1080p,Field-programmable gate array,Pixel,Encoding (memory) | Conference |
ISSN | Citations | PageRank |
1522-4880 | 3 | 0.38 |
References | Authors | |
5 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Thomas D'huys | 1 | 3 | 0.38 |
| Svetislav Momcilovic | 2 | 55 | 5.79 |
| Frederico Pratas | 3 | 119 | 15.69 |
| Leonel Sousa | 4 | 1210 | 145.50 |