Paper Info
Title
Benefits and costs of prediction based DVFS for NoCs at router level
Abstract
Power consumption remains one of the most important design objectives for network-on-chip (NoC) based systems. In this paper, we focus on the NoC component of these systems. Specifically, we introduce a new distributed dynamic voltage and frequency scaling (DVFS) algorithm that can tune the operation frequency and supply voltage of each router in the NoC dynamically in response to network load trends in order to mitigate network congestion and to reduce power consumption. The proposed distributed DVFS algorithm uses history based predictors that predict link and buffer utilizations. These predictions are used to forecast the future network load, which is used to also do proactive frequency tuning, thereby addressing potential congestion issues and reducing power consumption. When frequency throttle is used only, power consumption is reduced by up to 50% while the network latency is only slightly degraded. When frequency boost is also used, in addition to significant power reductions, network latency is also improved. We utilize the proposed DVFS algorithm as a testbed to gain new insights into the potential of DVFS for NoCs at router level.
Year
DOI
Venue
2014
10.1109/SOCC.2014.6948937
System-on-Chip Conference
Keywords
Field
DocType
network routing,network-on-chip,DVFS algorithm,NoC component,distributed dynamic voltage and frequency scaling algorithm,frequency boost,history based predictors,network congestion mitigation,network load,network-on-chip based systems,operation frequency,power consumption reduction,proactive frequency tuning,router level,supply voltage,congestion,dynamic voltage and frequency scaling,network-on-chip,power consumption,prediction
Network on a chip,Computer network,Frequency scaling,Engineering,Router,Power consumption,Embedded system
Conference
Citations 
PageRank 
References 
3
0.47
13
Authors
2
Name
Order
Citations
PageRank
Cristinel Ababei130.81
Nicholas Mastronarde224026.93