Title
An 8 Gb/s–64 Mb/s, 2.3–4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS
Abstract
A burst-mode transmitter achieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. The resistor tuning-based ring oscillator avoids the use of bias voltages and thereby eliminates the related settling time overhead. The calibrated rapid on-off biasing circuit utilizes a fast charging technique to achieve bias voltage settling time of 4 ns, resulting in 30X improvement over a diode-connected bias circuit. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32 byte long data bursts. We also present an analytical bit error rate (BER) computation technique for rapid on-off links, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10-12 BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively.
Year
DOI
Venue
2014
10.1109/JSSC.2014.2348317
Solid-State Circuits, IEEE Journal of  
Keywords
DocType
Volume
CMOS analogue integrated circuits,delay lock loops,error statistics,oscillators,BER computation technique,CMOS process,MDLL settling measurement data,always-on transmitter measurements,analytical bit error rate computation technique,bit rate 8 Mbit/s to 64 Mbit/s,burst-mode transmitter,current mode output driver,digital multiplying delay-locked loop,diode-connected bias circuit,energy efficiency,fast charging technique,fast frequency settling ring oscillator,rapid on-off biasing scheme,resistor tuning,size 90 nm,time 4 ns,time 6 ns,transmitter power consumption,Bit error rate,current mode logic (CML) output driver,digital multiplying delay-locked loop (MDLL),digitally-controlled ring oscillator (DCO),energy-proportional operation,fast turn-on clock multiplier,rapid on-off bias
Journal
49
Issue
ISSN
Citations 
10
0018-9200
0
PageRank 
References 
Authors
0.34
0
4
Name
Order
Citations
PageRank
Talegaonkar, M.100.34
Elshazly, A.200.34
Reddy, K.300.34
Prabha, P.400.34