Name
Abstract | ||
|---|---|---|
Multi-cores have become ubiquitous both in the general-purpose computing and the embedded domain. The current technology trends show that the number of on-chip cores is rapidly increasing, while their complexity is decreasing due to power and thermal constraints. Increasing number of simple cores enable parallel applications benefit from abundant thread-level parallelism (TLP), while sequential fragments suffer from poor exploitation of instruction-level parallelism (ILP). Recent research has proposed adaptive multi-core architectures that are capable of coalescing simple physical cores to create more complex virtual cores so as to accelerate sequential code. Such adaptive architectures can seamlessly exploit both ILP and TLP. The goal of this paper is to quantitatively characterize the performance potential of adaptive multi-core architectures. Previous research have primarily focused on only sequential workload on adaptive multi-cores. We address a more realistic scenario where parallel and sequential applications co-exist on an adaptive multi-core platform. Scheduling tasks on adaptive architectures reveal challenging resource allocation problems for the existing schedulers. We construct offline and online schedulers that intelligently reconfigure and allocate the cores to the applications so as to minimize the overall makespan under the constraints of a realistic adaptive multi-core architecture. Experimental results reveal that adaptive multi-core architectures can substantially decrease the makespan compared to both static symmetric and asymmetric multi-core architectures. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TC.2013.115 | Computers, IEEE Transactions |
Keywords | Field | DocType |
multi-threading,parallel architectures,resource allocation,scheduling,ILP,TLP,adaptive architectures,adaptive multicore architectures,core allocation,embedded domain,general-purpose computing,instruction-level parallelism,offline scheduler,on-chip cores,online scheduler,parallel applications,power constraints,resource allocation problems,sequential application,sequential code,sequential fragments,task scheduling,thermal constraints,thread-level parallelism,ILP,Scheduling,TLP,adaptive multi-cores,dynamic heterogeneous multi-core,malleable and moldable tasks | Instruction-level parallelism,Job shop scheduling,Computer science,Scheduling (computing),Workload,Task parallelism,Parallel computing,Exploit,Real-time computing,Resource allocation,Multi-core processor,Distributed computing | Journal |
Volume | Issue | ISSN |
63 | 10 | 0018-9340 |
Citations | PageRank | References |
17 | 0.65 | 22 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mihai Pricopi | 1 | 17 | 0.99 |
| Tulika Mitra | 2 | 2714 | 135.99 |