Title
FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board
Abstract
Even though FPGAs are becoming more and more popular as they are used in many different scenarios like communications and HPC, the steep learning curve needed to work with this technology is still the major limiting factor to their full success. Many works proposed to mitigate this problem by creating a companion of tools to support the designer during the development phase for this technology. The EU FASTER Project aims at realizing an integrated toolchain that assists the designer in the steps of the design flow that are necessary to port a given application onto an FPGA device. The novelty of the framework relies in the fact that the partial dynamic reconfiguration, which FPGA devices can exploit, is seen as a first class citizen throughout the whole design flow. This work reports a case study in which the FASTER toolchain has been used to port a raytracer application onto the STM Spear prototyping embedded platform. The paper discusses the steps done for the realization of the prototype and the results obtained on the target device. It finally reports some improvements that can be exploited to improve the performance of the hardware implementation that has been realized.
Year
DOI
Venue
2014
10.1109/ISPA.2014.26
Parallel and Distributed Processing with Applications
Keywords
Field
DocType
field programmable gate arrays,logic design,prototypes,FASTER toolchain,FPGA-based design,STM Spear prototyping embedded platform,hardware implementation,partial dynamic reconfiguration,raytracer application,partial reconfiguration
XML,First-class citizen,Computer science,Field-programmable gate array,Real-time computing,Design flow,Exploit,Graphical user interface,Control reconfiguration,Toolchain,Embedded system,Distributed computing
Conference
ISSN
Citations 
PageRank 
2158-9178
0
0.34
References 
Authors
7
4
Name
Order
Citations
PageRank
Spada, F.100.34
Scolari, A.200.34
Durelli, G.C.300.68
Riccardo Cattaneo4579.14