Paper Info
Title
Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering
Abstract
The High Efficiency Video Coding (HEVC) in-loop filtering is designed to reduce coding artifacts caused by image transforms and quantizations. HEVC in-loop filtering is divided to the Deblocking Filter and the Sample Adaptive Offset filter and these two filters take about 20% of total decoding time. This paper presents a very low-power (39mW) programmable coprocessor architecture to HEVC in-loop filtering, targeting especially embedded devices. The solution consists of three identical, tiny application specific instruction set processor cores which are able to process 30 Full-HD intra luma frames per second when the operating frequency is 350 MHz. The cores are fully programmable by C-language, which allows easy software modifications and updates. Although the cores have been designed for in-loop filtering, they are also capable of signal processing tasks that demand high performance. In terms of energy efficiency, the proposed architecture falls clearly between ASICs and conventional embedded processors, and thus forms a new-generation solution for HEVC in-loop filtering.
Year
DOI
Venue
2015
10.1109/TCSVT.2014.2369744
Circuits and Systems for Video Technology, IEEE Transactions  
Keywords
Field
DocType
hevc,video processing systems,in-loop filtering,multiprocessor architectures,application specific integrated circuits,decoding,multicore processing,energy efficiency,deblocking filter,encoding,coprocessors
Signal processing,Application-specific instruction-set processor,Computer science,Filter (signal processing),Coprocessor,Decoding methods,Multi-core processor,Deblocking filter,Embedded system,Encoding (memory)
Journal
Volume
Issue
ISSN
PP
99
1051-8215
Citations 
PageRank 
References 
6
0.51
21
Authors
4
Name
Order
Citations
PageRank
Ilkka Hautala1143.03
Jani Boutellier213725.36
Jari Hannuksela312113.36
Olli Silvén430338.76