Paper Info
Title
Efficient implementation for accurate analysis of CED circuits against multiple faults
Abstract
Reliability issues became an important concern in deep submicron CMOS devices. Concurrent Error Detection (CED) scheme has been proved to be an efficient technique in such a context. Different efforts were reported to quantify the efficiency of CED schemes but generally they consider single faults or suppose that implemented checker mechanisms are fault-free. This paper describes an alternative solution for CED circuits analysis, where the whole circuit (including checker mechanisms) is supposed to be fault prone. The proposed approach is based on Probabilistic Transfer Matrices and then can deal with multiple faults. The time efficiency of the proposed solution is demonstrated through arithmetic circuits.
Year
DOI
Venue
2014
10.1109/MIXDES.2014.6872236
MIXDES
Keywords
Field
DocType
cmos integrated circuits,error detection,integrated circuit reliability,matrix algebra,probability,ced circuit analysis,arithmetic circuits,checker mechanisms,concurrent error detection scheme,deep submicron cmos devices,multiple faults,probabilistic transfer matrices,reliability issues,concurrent error detection,reliability,logic gates,probabilistic logic,mathematical model
Computer science,Circuit extraction,Electronic engineering,Mixed-signal integrated circuit,Electronic circuit
Conference
Citations 
PageRank 
References 
1
0.35
12
Authors
4
Name
Order
Citations
PageRank
Ting An153.52
Kaikai Liu219020.37
Hao Cai36021.94
de Barros Naviner, L.A.410.35