Name
Abstract | ||
|---|---|---|
We propose a test-cube aware dynamic compaction method for reducing the test set size generated by scan ATPG. In the initial phase of ATPG, when the generated test cubes are significantly compatible, we start with a local cube merging approach. Then, we switch to a compacted cube-generation approach, when the compatibility of test cubes decrease. We propose efficient heuristics for merging test cubes and writing them out during the cube-merging phase. We introduce a novel reasoning analysis technique to learn cube-independent untestable faults and, avoid targeting them repeatedly during the compacted-cube generation phase. On latest Intel microprocessor designs, we are able to achieve up to 2.3X compaction with 20% run-time over-head, on top of on-chip hardware compression. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/VLSID.2014.24 | VLSI Design |
Keywords | Field | DocType |
automatic test pattern generation,Intel microprocessor designs,compacted-cube generation phase,on-chip hardware compression,reasoning analysis technique,scan ATPG,test-cube aware dynamic compaction method | Automatic test pattern generation,Dynamic compaction,Computer science,Parallel computing,Microprocessor,Real-time computing,Heuristics,Merge (version control),Compaction,Test set,Cube | Conference |
ISSN | Citations | PageRank |
1063-9667 | 1 | 0.36 |
References | Authors | |
10 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| S. Jha | 1 | 7921 | 539.19 |
| Chandrasekar, K. | 2 | 21 | 1.24 |
| Weixin Wu | 3 | 3 | 1.43 |
| R. Shankar | 4 | 1104 | 96.32 |