Paper Info
Title
A Reconfigurable MapReduce accelerator for multi-core all-programmable SoCs
Abstract
Phoenix MapReduce is a programming framework for multi-core systems that is used to automatically parallelize and schedule the programs based on the MapReduce framework. This paper presents a novel reconfigurable MapReduce accelerator that can be augmented to multi-core SoCs and it can speedup the indexing and the processing of the MapReduce key-value pairs. The proposed architecture is implemented, mapped and evaluated to an all-programmable SoC with two embedded ARM cores (Zynq FPGA). Depending on the MapReduce application requirements, the user can dynamically reconfigure the FPGA with the appropriate version of the MapReduce accelerator. The performance evaluation shows that the proposed scheme can achieve up to 2.3x overall performance improvement in MapReduce applications.
Year
DOI
Venue
2014
10.1109/ISSOC.2014.6972430
System-on-Chip
Keywords
Field
DocType
electronic engineering computing,field programmable gate arrays,multiprocessing systems,performance evaluation,programming,system-on-chip,ARM core,MapReduce key-value pair processing,Phoenix MapReduce,Zynq FPGA,field programmable gate array,multicore all-programmable SoC,multicore system,performance evaluation,program parallelization,program scheduling,programming framework,reconfigurable MapReduce accelerator,system-on-chip,MapReduce,Multi-core programming,scratchpad memory
Computer science,Parallel computing,Field-programmable gate array,Search engine indexing,Real-time computing,Multi-core processor,Software framework,Speedup,Performance improvement,Embedded system
Conference
Citations 
PageRank 
References 
4
0.43
4
Authors
3
Name
Order
Citations
PageRank
Christoforos Kachris124430.46
Sirakoulis, G.C.21149.55
Dimitrios Soudris324348.41