Paper Info
Title
A hybrid non-volatile SRAM cell with concurrent SEU detection and correction
Abstract
This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for SEU tolerance. The proposed NVSRAM cell consists of a 6T SRAM core and a Resistive RAM (RRAM), made of a 1T and a Programmable Metallization Cell (PMC). The proposed cell has concurrent error detection (CED) and correction capabilities; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation; data from the non-volatile memory element is copied back to the SRAM core. The dual-rail checker utilizes two XOR gates each made of 2 inverters and 2 ambipolar transistors, hence, it has a hybrid nature. Extensive simulation results are provided. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit such as delay and circuit complexity and thus applicable to integrated circuits such as FPGAs requiring secure on-chip non-volatile storage (i.e. LUTs) for multi-context configurability.
Year
DOI
Venue
2014
10.7873/DATE.2014.178
Design, Automation and Test in Europe Conference and Exhibition
Keywords
Field
DocType
SRAM chips,error detection,field programmable gate arrays,logic gates,radiation hardening (electronics),random-access storage,transistors,6T SRAM core,FPGA,LUT,PMC,SEU,XOR gates,ambipolar transistors,concurrent error detection,figures of merit,integrated circuits,inverters,nonvolatile SRAM cell,programmable metallization cell,resistive RAM,single event upset,Correction,Detection,Emerging Technology,Memory Cell,Programmable Metallization Cell (PMC),SEU
nvSRAM,Logic gate,Circuit complexity,Computer science,Parallel computing,Field-programmable gate array,XOR gate,Static random-access memory,Integrated circuit,Embedded system,Memory cell
Conference
ISSN
Citations 
PageRank 
1530-1591
2
0.38
References 
Authors
5
3
Name
Order
Citations
PageRank
Pilin Junsangsri1285.78
Fabrizio Lombardi21985259.25
Jie Han386366.92