Name
Abstract | ||
|---|---|---|
During the last years, SAT-based ATPG has been proved to be a powerful complement of traditional structural approaches. It outperforms structural methods when applied to hard-to-detect faults, and it can be combined with advanced SAT solving techniques in order to compute provably optimal solutions to complex test generation problems with optimisation goals. However, one weakness of SAT-based ATPG methods is their relatively high pattern count, which results largely from the over specification of the generated patterns. In order to overcome this weakness, we present a dynamic compaction technique specifically designed to work with SAT-based ATPG. We systematically investigate the impact of a conflict limit parameter and of several fault list sorting strategies on both test compactness and run-time. Using the best parameter combination, our SAT-based algorithm was able to generate with feasible computational effort more compact test sets for ISCAS circuits than a commercial structural tool, and the pattern counts for industrial circuits were reduced significantly. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/VLSID.2014.17 | VLSI Design |
Keywords | Field | DocType |
Boolean functions,automatic test pattern generation,computability,fault diagnosis,ISCAS,SAT-based ATPG method,SAT-based test pattern generation,advanced SAT solving technique,dynamic compaction technique,hard-to-detect fault,industrial circuit,optimisation | Boolean function,Automatic test pattern generation,Dynamic compaction,Fault coverage,Computer science,Algorithm,Computability,Compact space,Sorting,Electronic circuit | Conference |
ISSN | Citations | PageRank |
1063-9667 | 3 | 0.45 |
References | Authors | |
9 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alexander Czutro | 1 | 56 | 4.53 |
| Sudhakar M. Reddy | 2 | 5747 | 699.51 |
| Ilia Polian | 3 | 889 | 78.66 |
| Bernd Becker | 4 | 855 | 73.74 |