Name
Abstract | ||
|---|---|---|
This paper presents an architecture employing latched comparators and a time-to-digital converter to perform a logarithmic analog-to-digital conversion. Latched comparators are used to sample the input and reference signals and convert them to a time domain representation. A time-to-digital converter is then used to obtain the digital output word. The presented architecture eliminates input independent delays from the final quantization result. A transistor level implementation was simulated to confirm the feasibility of the architecture described in this paper. Monte Carlo and process corner simulation results are presented which confirms the feasibility of the architecture presented. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ICECS.2014.7049986 | Electronics, Circuits and Systems |
Keywords | Field | DocType |
Monte Carlo methods,comparators (circuits),delays,flip-flops,quantisation (signal),time-digital conversion,time-domain analysis,transistors,Monte Carlo simulation,digital output word,final quantization result,input independent delay elimination,input reference signals,latched comparators,logarithmic AD conversion,logarithmic analogue-digital conversion,process corner simulation,time domain representation,time-digital converter,transistor level implementation,analog-to-digital,logarithmic,time-to-digital,voltage-to-time | Time domain,Monte Carlo method,Comparator,Process corners,Computer science,Electronic engineering,Logarithm,Transistor,Quantization (signal processing),Electrical engineering,Time-to-digital converter | Conference |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mauro Santos | 1 | 3 | 1.86 |
| Nuno Cavaco Horta | 2 | 310 | 49.65 |
| Jorge Guilherme | 3 | 14 | 6.02 |