Name
Abstract | ||
|---|---|---|
This paper presents an infinite impulse response (IIR) temporal filtering technique for real-time stimulus artifact rejection (SAR) based on template subtraction. A system architecture for the IIR SAR algorithm is developed, and the operation of the algorithm with fixed-point computation is analyzed to obtain the number of bits for the internal nodes of the system, considering dynamic range and fraction length requirements for optimum performance. Further, memory initialization with the first recorded stimulus artifact is proposed and shown to significantly decrease the IIR system response time, especially when artifacts are highly reproducible in consecutive stimulation cycles. The proposed system architecture is hardware-implemented on a field-programmable gate array (FPGA) and tested using two sets of prerecorded neural data from a rat and an Aplysia californica (a marine sea slug) obtained from two different laboratories. The measured results from the FPGA verify that the system can indeed remove the stimulus artifacts from the contaminated neural data in real time and recover the neural action potentials that occur on the tail end of the artifact (as close as within 0.5 ms after the artifact spike). The root-mean-square (rms) value of the pre-processed stimulus artifact is reduced on average by a factor of 17 (Aplysia californica) and 5.3 (rat) post-processing. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TBCAS.2013.2274574 | Biomedical Circuits and Systems, IEEE Transactions |
Keywords | DocType | Volume |
IIR filters,bioelectric phenomena,field programmable gate arrays,medical signal processing,neurophysiology,Aplysia californica,IIR SAR algorithm,IIR temporal filtering,contaminated neural data,field programmable gate array,fixed point computation,infinite impulse response,internal nodes,marine sea slug,memory initialization,neural action potentials,rat,real time stimulus artifact rejection,template subtraction,Closed-loop neuroprostheses,field-programmable gate array (FPGA),neural recording,neurostimulation,stimulus artifact rejection,template subtraction | Journal | 8 |
Issue | ISSN | Citations |
3 | 1932-4545 | 1 |
PageRank | References | Authors |
0.40 | 8 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kanokwan Limnuson | 1 | 3 | 0.82 |
| Hui Lu | 2 | 8 | 1.16 |
| Hillel J. Chiel | 3 | 281 | 133.42 |
| Pedram Mohseni | 4 | 197 | 48.29 |