Name
Title | ||
|---|---|---|
A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems |
Abstract | ||
|---|---|---|
Cyber-Physical Systems need to handle increasingly complex tasks, which additionally, may have variable operating conditions over time. Therefore, dynamic resource management to adapt the system to different needs is required. In this paper, a new bus-based architecture, called ARTICo3, which by means of Dynamic Partial Reconfiguration, allows the replication of hardware tasks to support module redundancy, multi-thread operation or dual-rail solutions for enhanced side-channel attack protection is presented. A configuration-aware data transaction unit permits data dispatching to more than one module in parallel, or provide coalesced data dispatching among different units to maximize the advantages of burst transactions. The selection of a given configuration is application independent but context-aware, which may be achieved by the combination of a multi-thread model similar to the CUDA kernel model specification, combined with a dynamic thread/task/kernel scheduler. A multi-kernel application for face recognition is used as an application example to show one scenario of the ARTICo3 architecture. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/FPL.2014.6927394 | Field Programmable Logic and Applications |
Keywords | Field | DocType |
cryptography,face recognition,image processing,operating system kernels,parallel architectures,reconfigurable architectures,wireless sensor networks,ARTICo3 architecture,CUDA kernel model specification,adaptable bus architecture,configuration-aware data transaction unit,cyberphysical systems,data dispatching,dual-rail solutions,dynamic partial reconfiguration,dynamic resource management,face recognition,hardware tasks replication,module redundancy,multikernel application,multithread operation,sidechannel attack protection,Cyber-Physical Systems,Dependability,Dynamic and Partial Reconfiguration,FPGAs,Parallel processing,Wireless Sensor Networks | Resource management,Dependability,Computer science,CUDA,Parallel computing,Real-time computing,Thread (computing),Cyber-physical system,Redundancy (engineering),Fault tolerance,Control reconfiguration,Embedded system | Conference |
Citations | PageRank | References |
2 | 0.45 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Valverde, J. | 1 | 2 | 0.45 |
| Miguel A. Vega-Rodriguez | 2 | 145 | 18.81 |
| Camarero, J. | 3 | 2 | 0.45 |
| Andrés Otero | 4 | 73 | 8.56 |