Paper Info
Title
Low-power loop pipelining mapping onto CGRA utilizing variable dual VDD
Abstract
Coarse Grained Reconfigurable Architectures (CGRAs) are promising platform based on its high-performance and low cost. Researchers have developed efficient compilers for mapping compute-intensive applications on CGRA using modulo scheduling. In order to generate loop kernel, every stage of kernel are forced to have the same execution time which is determined by the critical PE. Hence non-critical PEs can decrease the supply voltage according to its slack time. The variable Dual-VDD CGRA incorporates this feature to reduce power consumption. Previous work mainly focuses on calculating a global optimal VDDL using overall optimization method that does not fully exploit the flexibility of architecture. In this paper, we adopt variable optimal VDDL in each stage of kernel concerning their pattern respectively instead of the fixed simulated global optimal VDDL. Experiment shows our proposed heuristic approach could reduce the power by 19.5% on average for the loops of GPS, MPEG2, H.264 and audio video coding standard (AVS) without decreasing performance. The additional compilation time is negligible. The area penalty of this method is less than 3%.
Year
DOI
Venue
2014
10.1109/MWSCAS.2014.6908397
Circuits and Systems
Keywords
DocType
ISSN
field programmable gate arrays,program compilers,reconfigurable architectures,scheduling,AVS,CGRA,GPS,H.264,MPEG2,audio video coding standard,coarse grained reconfigurable architectures,compilers,compute-intensive mapping,field programmable gate arrays,fixed simulated global optimal voltage,loop kernel generation,low-power loop pipelining mapping,modulo scheduling,noncritical PEs,optimization method,power consumption reduction,variable dual voltage,CGRA,Dual-VDD,Loop Mapping,Low-Power,Software Pipelinning
Conference
1548-3746
Citations 
PageRank 
References 
0
0.34
0
Authors
4
Name
Order
Citations
PageRank
Bin Xu113323.23
shouyi yin257999.95
leibo liu3816116.95
Shaojun Wei4555102.32