Name
Abstract | ||
|---|---|---|
A 0.6V 10-bit 150MS/s single-channel asynchronous subranging SAR ADC using a settling-time relief technique is presented. The technique extends the allocated DAC settling time with the assistance of a coarse ADC and minimizes digital loop delay so that it can reach high speed and low power at a 0.6V supply. This ADC consumes 0.264mW at 150MS/s in 40nm CMOS technology. It achieves an SNDR of 50.5dB at Nyquist rate and results in an FoM of 6.4fJ/c.-s. The core circuit only occupies an area of 0.0063 mm2. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ASSCC.2014.7008865 | A-SSCC |
Keywords | Field | DocType |
cmos digital integrated circuits,analogue-digital conversion,asynchronous circuits,low-power electronics,cmos technology,nyquist rate,conversion-step subranging sar,digital loop delay,power 0.264 mw,settling-time relief technique,single-channel asynchronous subranging sar adc,size 40 nm,voltage 0.6 v,word length 10 bit,analog to digital converter (adc),settling time,subranging,successive approximation register (sar),switches,cmos integrated circuits,noise,capacitors,redundancy | Asynchronous communication,Capacitor,Settling time,Computer science,CMOS,Electronic engineering,Real-time computing,Redundancy (engineering),Successive approximation ADC,Nyquist rate,Electrical engineering | Conference |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yao-Sheng Hu | 1 | 44 | 5.40 |
| Chi-Huai Shih | 2 | 0 | 0.34 |
| Hung-Yen Tai | 3 | 61 | 8.18 |
| Hung-Wei Chen | 4 | 151 | 16.28 |