Name
Title | ||
|---|---|---|
An 8-bit 0.35-V 5.04-fJ/Conversion-Step SAR ADC With Background Self-Calibration of Comparator Offset |
Abstract | ||
|---|---|---|
This paper reports a successive approximation register (SAR) analog-to-digital converter (ADC) based on the charge-sharing principle, which is known to be very energy efficient, but susceptible to the comparator offset. The ADC uses a new background calibration technique to cancel out the comparator mismatch and improve ADC linearity. Operation under low voltages is obtained through the use of voltage-boosted switches in the track-and-hold and the digital-to-analog converter. The techniques are demonstrated on a low-voltage low-power SAR ADC that operates from a minimum supply voltage of 350 up to 600 mV, suitable for circuits supplied by power harvesters. The prototype fabricated in a 130-nm CMOS process employs only regular- transistors. It is able to convert at 3 MSps when supplied by 600 mV and at 200 kSps when supplied by 350 mV. At 350 mV, the measured effective-number-of-bits is 6.4, leading to a figure-of-merit of 5.04 fJ/conversion-step. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/TVLSI.2014.2337236 | VLSI) Systems, IEEE Transactions |
Keywords | DocType | Volume |
analog-to-digital converter (adc),charge sharing (cs),comparator calibration,low voltage,successive approximation register (sar),cmos integrated circuits,transistors,complementary metal oxide semiconductor,figure of merit,noise,calibration,capacitors,logic gates,topology | Journal | PP |
Issue | ISSN | Citations |
99 | 1063-8210 | 9 |
PageRank | References | Authors |
0.71 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Taimur Gibran Rabuske | 1 | 28 | 6.53 |
| Fabio Alex Rabuske | 2 | 9 | 1.38 |
| Jorge R. Fernandes | 3 | 154 | 34.16 |
| Cesar Ramos Rodrigues | 4 | 30 | 7.05 |