Name
Title | ||
|---|---|---|
A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI |
Abstract | ||
|---|---|---|
A 20 GS/s 6b time-interleaved ADC is implemented in 32 nm CMOS SOI with an embedded time-to-digital converter to sense timing skew, and the randomness of process mismatch is exploited to compensate for the clock misalignment and dynamic offset errors of comparators that occur during high-speed operation. To achieve low-power consumption at high-speed operation with small-size transistors, a low-complexity on-chip calibration reduces gain, offset, and delay mismatches in background. With the timing skew calibration, the spurs due to clock misalignment are reduced by 20 dB. The proposed ADC achieves an SNDR of 30.7 dB at Nyquist frequency and consumes only 69.5 mW with a figure-of-merit of 124 J/conv-step. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/JSSC.2014.2364043 | Solid-State Circuits, IEEE Journal of |
Keywords | DocType | Volume |
CMOS integrated circuits,calibration,low-power electronics,silicon-on-insulator,time-digital conversion,timing,CMOS SOI,clock misalignment,comparators,dynamic offset errors,embedded time-to-digital converter,low-complexity on-chip calibration,low-power consumption,power 69.5 mW,process mismatch randomness,size 32 nm,time-interleaved ADC,timing skew calibration,ADC,background calibration,gain calibration,high speed,low power,mismatch,offset calibration,time-interleaving,timing skew calibration | Journal | 49 |
Issue | ISSN | Citations |
12 | 0018-9200 | 4 |
PageRank | References | Authors |
0.53 | 0 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chen, V.H.-C. | 1 | 5 | 2.66 |
| Lawrence T. Pileggi | 2 | 9 | 2.71 |