Name
Abstract | ||
|---|---|---|
The increasing performance demand in the critical real-time embedded systems (CRTES) domain calls for high-performance features such as cache memories. Unfortunately, the cost to provide trustworthy and tight Worst-Case Execution Time (WCET) estimates in the presence of caches is high with current practice WCET analysis tools, because they need detailed knowledge of program’s cache accesses to provide tight WCET estimates. The advent of Probabilistic timing analysis (PTA) opens the door to economically viable timing analysis in the presence of caches, but it imposes new requirements on hardware design. At cache level, so far only fully associative random-replacement caches have been proven to fulfill the needs of PTA, but their energy, delay, and area cost are unaffordable for CRTES. In this paper, we propose the first PTA-compliant cache design based on set-associative and direct-mapped arrangements, as those are the most common arrangements. In particular, we propose a novel parametric random placement policy suitable for PTA that is proven to have low hardware complexity and energy consumption while providing comparable performance to that of conventional modulo placement. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TC.2013.182 | Computers, IEEE Transactions |
Keywords | Field | DocType |
cache storage,circuit complexity,content-addressable storage,embedded systems,probability,CRTES domain,PTA-compliant cache design,WCET analysis tools,cache memories,critical real-time embedded systems,direct-mapped arrangements,energy consumption,hardware complexity,hardware design,high-performance features,parametric random placement policy,probabilistic timing analysis,probabilistically analysable real-time systems,program cache accesses,set-associative arrangements,trustworthy-tight WCET estimates,trustworthy-tight worst-case execution time estimates,Cache memories,worst-case analysis | Cache invalidation,Cache pollution,Computer science,Cache,Parallel computing,Cache algorithms,Real-time computing,Static timing analysis,Cache coloring,Smart Cache,Energy consumption,Embedded system | Journal |
Volume | Issue | ISSN |
63 | 12 | 0018-9340 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Leonidas Kosmidis | 1 | 418 | 28.48 |
| Jaume Abella | 2 | 1046 | 76.34 |
| E. Quinones | 3 | 77 | 4.71 |
| Francisco J. Cazorla | 4 | 151 | 7.82 |