Name
Title | ||
|---|---|---|
A bidirectional neural interface SoC with an integrated spike recorder, microstimulator, and low-power processor for real-time stimulus artifact rejection |
Abstract | ||
|---|---|---|
This paper presents a neural interface system-on-chip (SoC) featuring combined spike recording, electrical microstimulation, and real-time stimulus artifact rejection (SAR) for bidirectional interfacing with the nervous system. The SoC integrates a spike-recording front-end with input noise voltage of 3.42 μVrms (0.5 Hz---50 kHz), microstimulating back-end for delivering charge-balanced monophasic or asymmetric biphasic current pulses of <100 μA with passive discharge, and μW-level digital signal processing (DSP) unit for real-time SAR based on template subtraction. The DSP unit initializes its embedded 16b, 4 K static random-access memory with the first recorded stimulus artifact to reduce the operation time in generating an accurate artifact template signal for subtraction. Fabricated in AMS 0.35 μm 2P/4M CMOS, the 3.1 × 3.1-mm2 SoC has been characterized in benchtop tests and neurobiological experiments with isolated buccal ganglia of an Aplysia californica (a marine mollusk). The SoC can successfully remove mV-range stimulus artifacts with duration up to ~115 ms from the contaminated neural data in real time and recover µV-range extracellular neural spikes that occur on the tail end of the artifacts. The average root-mean-square (rms) value of the pre-processed stimulus artifact is reduced by a factor of ~24---30 post-processing, with DSP unit power consumption of <25 µW from 1.5 V. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/CICC.2014.6946129 | Analog Integrated Circuits and Signal Processing |
Keywords | Field | DocType |
CMOS integrated circuits,lab-on-a-chip,low-power electronics,microprocessor chips,neural chips,neurophysiology,system-on-chip,AMS 2P/4M CMOS,Aplysia catifornica,asymmetric biphasic current pulses,bidirectional interfacing,bidirectional neural interface SoC,central nervous system,charge-balanced monophasic current pulses,contaminated neural data,digital signal processing unit,electrical microstimulation,extracellular neural spikes,frequency 0.5 Hz to 50 kHz,integrated spike recorder,isolated buccal ganglia,low-power processor,marine sea slug,microstimulator,neural interface system-on-chip,neurobiological experiments,passive discharge,real-time stimulus artifact rejection,root-mean-square value,size 0.35 mum,spike recording,spike-recording front-end,template subtraction | Digital signal processing,System on a chip,Microstimulation,Computer science,Voltage,Brain–computer interface,Interfacing,Electronic engineering,CMOS,Computer hardware,Subtraction | Conference |
Volume | Issue | ISSN |
82 | 2 | 0925-1030 |
Citations | PageRank | References |
2 | 0.42 | 6 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kanokwan Limnuson | 1 | 3 | 0.82 |
| Lu, H. | 2 | 2 | 0.42 |
| Hillel J. Chiel | 3 | 281 | 133.42 |
| Pedram Mohseni | 4 | 197 | 48.29 |