Name
Title | ||
|---|---|---|
Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating |
Abstract | ||
|---|---|---|
This paper describes a new approach to reduce the ground bounce (GB) while keeping the wakeup time short for fine-grain power gating. We propose a novel algorithm to synthesize an optimal unbalanced buffer tree (UBT) that turns on parallel power switches with slight time differences. We have applied our algorithm to function units of a 32-bit microprocessor. Experimental results have revealed that our UBT gives better solution than the conventional daisy-chain approach in the space of wakeup time and GB. For example, in the ALU, our UBT suppressed the maximum GB voltage to 16mV which is 24% smaller than that of the parallel daisy chain, while keeping the wakeup time 0.6ns. In the 32b×32b multiplier, our UBT suppressed GB by 32% lower than the daisy chain but still kept the wakeup time 0.7ns. The microprocessor test chip with our UBT technique is successfully under operation. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ISSOC.2014.6972438 | System-on-Chip |
Keywords | Field | DocType |
buffer circuits,low-power electronics,microprocessor chips,daisy chain,fine grain power gating,ground bounce,microprocessor test chip,parallel power switches,unbalanced buffer tree synthesis,wakeup time,ground bounce,low power,power gating | Ground bounce,Computer science,Microprocessor,Parallel computing,Voltage,Daisy chain,Chip,Multiplier (economics),Real-time computing,Power gating | Conference |
Citations | PageRank | References |
1 | 0.36 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Usami, K. | 1 | 1 | 0.36 |
| Miyauchi, M. | 2 | 1 | 0.36 |
| Masaru Kudo | 3 | 17 | 2.94 |
| Takagi, K. | 4 | 5 | 1.25 |