Name
Abstract | ||
|---|---|---|
The design of the 68040, a third-generation, full-32-b microprocessor in the Motorola 68000 family, is presented. The 68040 integrates over 1.2 million transistors on one chip and can execute the complete 68020 microprocessor and 68882 floating-point coprocessor instruction sets. Pipelined integer and floating-point execution units that operate concurrently with separate internal memory controllers and an autonomous bus controller contribute to its high performance level. Physical caches of 4 kB each for instruction and data reside on chip. Separate address-translation caches of 64 entries apiece operate in parallel with the instruction and data caches. This arrangement provides complete memory management in a virtual, demand-paged operating system. The design team explains its total approach and the workings of the integer and floating-point units. |
Year | DOI | Venue |
|---|---|---|
1990 | 10.1109/40.46770 | IEEE Micro |
Field | DocType | Volume |
Instruction set,Computer science,Microprocessor,Parallel computing,Motorola 68851,Chip,Memory management,Coprocessor,Memory controller,Operating system,Control bus | Journal | 10 |
Issue | ISSN | Citations |
1 | 0272-1732 | 9 |
PageRank | References | Authors |
1.94 | 2 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Robin W. Edenfield | 1 | 12 | 3.31 |
| Michael G. Gallup | 2 | 30 | 10.14 |
| William Ledbetter Jr. | 3 | 12 | 3.31 |
| Ralph C. McGarity | 4 | 24 | 7.17 |
| Eric E. Quintana | 5 | 12 | 3.65 |
| Russel A. Reininger | 6 | 12 | 3.31 |