Name
Abstract | ||
|---|---|---|
The sensitivity of delay time (time required to achieve a given target voltage) at any node of a nonlinear monotone RC tree is studied using the adjoint-network approach. It is shown that the sensitivity of τ with respect to changes in a parameter of the resistors or the capacitors of the tree can be expressed as an integral of the solutions of the network and its adjoint network. Using this integral it is then established that τ increases for some nodes (depending upon location of a node) due to the decrease in a given resistor value, when τ is small. For other nodes τ would decrease. However, if the target voltage is close to the steady-state value then τ decreases for all the nodes |
Year | DOI | Venue |
|---|---|---|
1990 | 10.1109/43.55176 | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions |
Keywords | DocType | Volume |
delays,nonlinear network analysis,sensitivity analysis,adjoint-network approach,capacitors,delay time sensitivity,nonlinear monotone RC trees,resistors | Journal | 9 |
Issue | ISSN | Citations |
5 | 0278-0070 | 1 |
PageRank | References | Authors |
0.43 | 2 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| N. K. Jain | 1 | 1 | 0.43 |
| Prasad, V.C. | 2 | 1 | 0.43 |
| Bhattacharyya, A.B. | 3 | 1 | 0.43 |