Name
Abstract | ||
|---|---|---|
Two techniques for compiled unit-delay simulation have been presented. These are a PC-set (the set of potential change times) method and a parallel technique. The PC-set method analyzes a network, determines a set of potential change times for each net, and generates gate simulations for each potential change. The parallel technique, which is based on a concept of parallel fault simulation, is faster and generates less code than the PC-method, but it is less flexible. Benchmark comparisons with an interpreted event-driven simulation show a factor of four improvement for the PC-set method and a factor of ten improvement for the parallel technique |
Year | DOI | Venue |
|---|---|---|
1990 | 10.1109/DAC.1990.114903 | DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference |
Keywords | Field | DocType |
fault location,logic CAD,PC-set,benchmark comparison,event-driven simulation,gate simulations,parallel fault simulation,parallel technique,unit-delay compiled simulation | Computer science,Parallel computing,Real-time computing,Event driven simulation,Discrete event simulation | Conference |
ISSN | ISBN | Citations |
0738-100X | 0-89791-363-9 | 18 |
PageRank | References | Authors |
2.27 | 7 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Peter M. Maurer | 1 | 133 | 22.43 |
| Zhicheng Wang | 2 | 176 | 17.00 |