Paper Info
Title
Multiplexing test system channels for data rates above 1 Gb/s
Abstract
The author describes high-speed digital circuits appropriate for use in testing devices at data rates above 1 Gb/s. A system which combines several test channels to form a smaller number of higher frequency data sources is described. Each combination of channels provides software-programmable data streams which are used as input stimuli to the device under test (DUT). The responses of DUT outputs are tested at high frequency through multipass monitoring of DUT outputs with existing comparators. Initial experiments have demonstrated the feasibility of this approach at rates above 1 Gb/s using digital GaAs logic. Burst rates above 2 Gb/s have also been achieved. The methods described are widely applicable to a variety of high-speed component technologies, including submicrometer CMOS, emitter-coupled logic, and GaAs
Year
DOI
Venue
1990
10.1109/TEST.1990.114043
Washington, DC
Keywords
Field
DocType
III-V semiconductors,VLSI,automatic test equipment,computer architecture,digital integrated circuits,electronic equipment testing,gallium arsenide,integrated circuit testing,integrated logic circuits,logic testing,multiplexing equipment,1 to 2 Gbit/s,GaAs,emitter-coupled logic,high-speed digital circuits,software-programmable data streams,submicrometer CMOS
Digital electronics,Device under test,Comparator,System testing,Computer science,Automatic test equipment,Emitter-coupled logic,Electronic engineering,CMOS,Multiplexing
Conference
Citations 
PageRank 
References 
9
1.35
12
Authors
1
Name
Order
Citations
PageRank
David C. Keezer1459.64