Name
Abstract | ||
|---|---|---|
Wafer-scale integration architecture for rapid prototyping (WARP), a generalized architecture for rapid prototyping, is discussed. The primary goal of rapid prototyping is to map one of several members of a class of algorithms using a single-wafer architecture. The wafer can be personalized for the algorithm by either soft or hard-restructuring. The WARP wafer consists of an array of two types of cells specifically defined for this architecture: the universal multiply-subtract-add (UMSA) cell and the universal nonlinear (UNL) cell. Reconfiguration of the algorithms in the presence of defects, a harvesting probability model and yield, and wafer-scale testing and test facilities are described.<> |
Year | DOI | Venue |
|---|---|---|
1992 | 10.1109/2.129054 | IEEE Computer |
Keywords | DocType | Volume |
VLSI,computer architecture,WARP,WSI,harvesting probability model,rapid prototyping,single-wafer architecture,universal multiply-subtract-add,wafer-scale testing,yield | Journal | 25 |
Issue | ISSN | Citations |
4 | 0018-9162 | 5 |
PageRank | References | Authors |
1.06 | 1 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vijay Jain | 1 | 50 | 13.06 |
| Hiroomi Hikawa | 2 | 7 | 1.45 |
| David C. Keezer | 3 | 45 | 9.64 |