Name
Abstract | ||
|---|---|---|
The Motorola 68040 floating point unit (FPU) combines three independent state machines, two data paths, and over 100000 transistors to achieve 8-Mflops peak performance and over 3-Mflops Linpack double-precision performance at the introductory speed of 25 MHz. It is optimized for minimum latency and maximum pipelined performance on frequently used double-precision floating point instructions. The FPU is architecturally divided into three piped stages, the conversion unit (CU), the execution unit (XU), and the normalization unit (NU). The control logic is tested using scan to achieve very high ATPG fault coverage while the data paths are tested using functional patterns |
Year | DOI | Venue |
|---|---|---|
1990 | 10.1109/ICCD.1990.130198 | ICCD |
Keywords | Field | DocType |
computer architecture,microprocessor chips,pipeline processing,25 mhz,3 mflops,3-mflops linpack double-precision performance,8 mflops,8-mflops peak performance,atpg fault coverage,motorola 68040,control logic,conversion unit,data paths,double-precision floating point instructions,execution unit,floating point unit,functional patterns,maximum pipelined performance,minimum latency,normalization unit,floating point,state machine,fault coverage,pipelines,hardware,automatic test pattern generation,coprocessors,floating point arithmetic | Automatic test pattern generation,Fault coverage,Floating point,Computer science,Floating-point unit,Parallel computing,Arithmetic logic unit,Real-time computing,Control logic,Coprocessor,Execution unit | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| shawn mccloud | 1 | 0 | 0.34 |
| donnie anderson | 2 | 0 | 0.34 |
| chris dewitt | 3 | 0 | 0.34 |
| chris n hinds | 4 | 0 | 0.34 |
| yingwai ho | 5 | 0 | 0.34 |
| daniel t marquette | 6 | 0 | 0.34 |
| Eric E. Quintana | 7 | 12 | 3.65 |