Name
Abstract | ||
|---|---|---|
The article introduces a new high-level synthesis method for self-testable RTL designs. A basic feature of this method is a structural testability model which treats testability as a structural design style integrated in the design process. The main objective is to develop a system-level synthesis tool set mapping a behavioral description onto an optimized and testable RTL design subject to user-defined constraints. The approach involves several major components within the following system-level iteration: scheduling and allocation, constraint estimation, and testability tradeoffs |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1109/ICCD.1991.139947 | Cambridge, MA |
Keywords | DocType | ISBN |
built-in self test,integrated circuit testing,logic testing,SYNTEST,allocation,behavioral description,constraint estimation,high-level SYNthesis,scheduling,self-testable RTL designs,structural design style,structural testability model,system-level synthesis tool set,testability tradeoffs,user-defined constraints | Conference | 0-8186-2270-9 |
Citations | PageRank | References |
19 | 1.29 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| C. Papachristou | 1 | 421 | 49.23 |
| Scott Chiu | 2 | 199 | 16.59 |
| Haidar M. Harmanani | 3 | 179 | 19.13 |