Name
Abstract | ||
|---|---|---|
The heterogeneous vision architecture that satisfies the computing demands of real-time computer vision by providing parallelism in three different forms is described. A pipeline of digital signal processing (DSP) chips initially processes signals. Then a SIMD associative processor array processes images and extract features, and a MIMD network of transputers processes extracted objects in parallel. The array's VLSI implementation, the processing modes available due to the use of content-addressable memory, and the means of achieving efficient 2-D interprocessor communication in the linear array are described. An application as a vehicle number plate recognition system is presented. |
Year | DOI | Venue |
|---|---|---|
1992 | 10.1109/40.141602 | IEEE Micro |
Field | DocType | Volume |
Digital signal processing,Architecture,Computer architecture,Computer science,Parallel computing,SIMD,Interprocessor communication,Computer hardware,Digital image processing,Very-large-scale integration,Associative processing,MIMD | Journal | 12 |
Issue | ISSN | Citations |
3 | 0272-1732 | 3 |
PageRank | References | Authors |
0.50 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Richard H. Storer | 1 | 3 | 0.50 |
| Mike R. Pout | 2 | 3 | 1.18 |
| Andrew R. Thomson | 3 | 8 | 2.81 |
| Erik L Dagless | 4 | 26 | 7.29 |
| Andrew W. G. Duller | 5 | 3 | 1.52 |
| Paul Marriott | 6 | 3 | 0.50 |
| Peter J. Hicks | 7 | 3 | 0.50 |