Name
Abstract | ||
|---|---|---|
The space-time representation approach is extended to map algorithms with complex operations into systolic arrays. Several new techniques are proposed, including algorithm refinement and hardware sharing in the processing elements of the systolic arrays. Compared to existing techniques, the proposed method provides a simple and efficient approach to reducing the complexity of the processing element design and achieving higher throughput |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1109/GLSV.1991.143967 | Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
VLSI,logic CAD,systolic arrays,VLSI systolic arrays,algorithm refinement,complex processing elements,hardware sharing,space-time representation | Computer architecture,MISD,Computer science,Processing element,Throughput,Very-large-scale integration | Conference |
Citations | PageRank | References |
2 | 0.60 | 2 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| C. N. Zhang | 1 | 28 | 6.89 |
| Alen George Law | 2 | 4 | 1.15 |
| Rezazadeh, A. | 3 | 4 | 1.15 |