Name
Abstract | ||
|---|---|---|
Pipelined structures based on the residue number system (RNS) have been found suitable for high-speed arithmetic. The polynomial RNS (PRNS) can speed up digital signal processing (DSP)-related tasks like correlations and convolutions. The authors introduce pipelined arrays able to serve as mapping modules for PRNS-based functional units. Such mappings, involve polynomial evaluation coupled with modulo operations. The authors show how VLSI array processors can perform modulo operations in a parallel environment. A methodology is presented by which the reliability of such fast architectures can be ensured simply by probing into the mechanics of the computations involved. The proposed techniques provide a hardware base for PRNS implementations. At the same time, a reasonable degree of fault-tolerance can be guaranteed in the face of high system throughputs |
Year | DOI | Venue |
|---|---|---|
1990 | 10.1109/ASAP.1990.145468 | Physica B-condensed Matter |
Keywords | DocType | Citations |
vlsi,computerised signal processing,digital arithmetic,fault tolerant computing,parallel architectures,pipeline processing,vlsi array processors,convolutions,correlations,digital signal processing,fast architectures,fault-tolerance,high-speed arithmetic,linear arrays,mapping modules,modulo operations,parallel environment,pipelined arrays,polynomial rns,residue mappers,residue number system,application software,logic,computer architecture,polynomials,application specific integrated circuits,very large scale integration,fault tolerance | Conference | 0 |
PageRank | References | Authors |
0.34 | 1 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| zarir b sarkari | 1 | 0 | 0.34 |
| Alexander Skavantzos | 2 | 29 | 6.50 |