Name
Abstract | ||
|---|---|---|
The authors present an approach for the analytical timing model development of bipolar VLSI circuits. The approach is based on the development of the delay functions of three basic bipolar subcircuits. It is shown that accurate timing information for two high-speed digital circuit constructs, ECL (emitter coupled logic) and BiCMOS, can be obtained by repeated processing of these subcircuit delay functions. The timing models have been shown to be accurate typically within 10% of SPICE's estimates with up to three orders of speedup for large-scale BJT (bipolar junction transistor) circuits.<> |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1109/ICCAD.1991.185274 | Santa Clara, CA, USA |
Keywords | Field | DocType |
BIMOS integrated circuits,VLSI,bipolar integrated circuits,circuit analysis computing,emitter-coupled logic,BiCMOS,ECL,analytical timing model,bipolar VLSI circuits,delay functions,emitter coupled logic,high-speed digital circuit constructs,interconnects,parametric correction | BiCMOS,Digital electronics,Computer science,Emitter-coupled logic,Electronic engineering,Resistor–transistor logic,Bipolar junction transistor,Mixed-signal integrated circuit,Logic family,Integrated injection logic | Conference |
Citations | PageRank | References |
3 | 0.56 | 1 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. T. Yang | 1 | 145 | 35.28 |
| Chang, Y.-H. | 2 | 5 | 0.96 |