Name
Abstract | ||
|---|---|---|
This paper presents a design of a low-voltage analog current detector supporting the at-speed Built-In-Self-Test (BIST) methodology. In testing mode, the current detector performs a non-functional Iddq and delta Iddq test which enables a more accurate fail/pass decision. A 1.2 V high-frequency current amplifying cell is utilized. With a sensitivity of less than 200 nA, the detector achieves a wide gain-bandwidth product of 6.8 GHz and the low frequency current gain of 48 dB. The operation of the detector has been verified experimentally. The current detector has been implemented in 0.13 μm CMOS technology. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ISCAS.2002.1009910 | Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium |
Keywords | Field | DocType |
CMOS integrated circuits,analogue integrated circuits,built-in self test,detector circuits,fault location,integrated circuit testing,leakage currents,mixed analogue-digital integrated circuits,wideband amplifiers,0.13 micron,1.2 V,48 dB,CMOS technology,HF current amplifying cell,LV analog current detector,SoC test applications,analog cores,at-speed BIST methodology,built-in-self-test methodology,delta Iddq test,fail/pass decision,leakage currents,low-voltage current detector,mixed-signal cores,nonfunctional Iddq test | Low frequency,Computer science,System testing,CMOS,Electronic engineering,Iddq testing,Low voltage,Analog computer,Electrical engineering,Detector,Built-in self-test | Conference |
Volume | Citations | PageRank |
1 | 5 | 0.78 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Srdjan Dragic | 1 | 5 | 0.78 |
| Igor Filanovsky | 2 | 21 | 8.68 |
| Martin Margala | 3 | 318 | 55.78 |