Name
Abstract | ||
|---|---|---|
A VLSI architecture dedicated to W-CDMA (Wideband Code Division Multiple Access) baseband modem is de- scribed, with the main theme focused on the cell searcher and PIL (Prime InterLeaver). A search algorithm is refined for the cell searcher to minimize the circuit size, maintain- ing the operating throughput. In addition, a time-shared scheme is adopted for the Turbo encoding/decoding, aim- ing at the maximization of the hardware sharing in the en- coding/decoding process. Finally, implementation results are shown to demonstrate that the proposed architecture can contribute much toward the practical low-power implemen- tation of W-CDMA baseband modem LSI. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ISCAS.2002.1010212 | Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium |
Keywords | DocType | Volume |
CMOS digital integrated circuits,VLSI,application specific integrated circuits,code division multiple access,decoding,digital filters,digital radio,digital signal processing chips,low-power electronics,matched filters,mobile radio,telecommunication computing,turbo codes,100 MHz,VLSI architecture,W-CDMA baseband modem,cell searcher,digital matched filter,hardware sharing,low-power implementation,modem LSI,operating throughput,prime interleaver,search algorithm,time-shared scheme,turbo encoding/decoding,wideband CDMA,wideband code division multiple access | Conference | 3 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Uchida, Y. | 1 | 0 | 0.34 |
| Ise, M. | 2 | 0 | 0.34 |
| T. Onoye | 3 | 37 | 10.36 |
| Isao Shirakawa | 4 | 220 | 65.34 |