Name
Abstract | ||
|---|---|---|
A digital-chip architecture for a 106-synapse neural network is proposed. It runs on a 1.5-V dry cell to allow its use in portable equipment. An on-chip DRAM cell array stores synapse weights digitally to provide easy programmability and automatic refreshing. A pitch-matched interconnection and a combinational unit circuit for summing product allow a tight layout. A dynamic data transfer circuit and the 1.5-V operation of the entire chip reduce the power dissipation, but the parallel processing nonetheless provides high speed at the 1.5-V supply. Estimated power dissipation of 75 mW and a processing speed of 1.37 giga connections per second are predicted for the chip. The memory and the processing circuits can be integrated on a 15.4-mm×18.6-mm chip by using a 0.5-μm CMOS design rule. A scaled-down version of the chip that has an 8-kb DRAM cell array was fabricated, and its operation was confirmed |
Year | DOI | Venue |
|---|---|---|
1993 | 10.1109/72.217179 | IEEE Transactions on Neural Networks |
Keywords | DocType | Volume |
neural network,combinational unit circuit,parallel processing,CMOS integrated circuits,synapse weights,power dissipation,106-synapse,1.5 v,CMOS design rule,interconnection,dynamic data transfer circuit,75 mW,DRAM chips,summing product,single-chip architecture,data transfer circuit,programmability,automatic refreshing,digital-chip architecture,pitch-matched interconnection,VLSI,0.5 micron,on-chip DRAM cell array,portable equipment,neural chips | Journal | 4 |
Issue | ISSN | Citations |
3 | 1045-9227 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| T. Watanabe | 1 | 252 | 51.28 |
| Kimura, Katsutaka | 2 | 0 | 0.34 |
| Aoki, M. | 3 | 0 | 0.68 |
| Sakata, T. | 4 | 18 | 4.26 |