Name
Abstract | ||
|---|---|---|
The Gmicro/500, which features a RISC-like dual-pipeline structure for high-speed execution of basic instructions and represents a significant advance for the TRON architecture, is presented. Upwardly-object-compatible with earlier members of the Gmicro series, this microprocessor uses resident dedicated branch buffers to greatly enhance branch instruction execution speed. Its microprograms simultaneously use dual execution blocks to execute high-level language instructions effectively. Fabricated with a 0.6- mu m CMOS technology on a 10.9-mm*16-mm die, the chip operates at 50/66 MHz and achieves a processing rate of 100/132 MIPS. |
Year | DOI | Venue |
|---|---|---|
1993 | 10.1109/40.237998 | IEEE Micro |
Field | DocType | Volume |
Pipeline (computing),Architecture,Computer architecture,Computer science,Microprocessor,Parallel computing,CMOS,Chip,Real-time computing,Reduced instruction set computing,Superscalar | Journal | 13 |
Issue | ISSN | Citations |
5 | 0272-1732 | 2 |
PageRank | References | Authors |
0.42 | 5 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kunio Uchiyama | 1 | 62 | 15.43 |
| Fumio Arakawa | 2 | 34 | 13.44 |
| Susumu Narita | 3 | 8 | 4.10 |
| Hirokazu Aoki | 4 | 2 | 1.09 |
| Ikuya Kawasaki | 5 | 71 | 10.03 |
| Shigezumi Matsui | 6 | 2 | 0.42 |
| Mitsuyoshi Yamamoto | 7 | 45 | 2.66 |
| Norio Nakagawa | 8 | 13 | 6.54 |
| Ikuo Kudo | 9 | 22 | 6.03 |