Name
Title | ||
|---|---|---|
Parallel switch level fault simulation algorithm/complexity verification using compiled code VHDL |
Abstract | ||
|---|---|---|
Switch level faults, as opposed to traditional gate level faults, can more accurately model the physical faults found in integrated circuits. Existing fault simulation techniques have a worst-case computational complexity of O(n**2), where n is the number of devices in the circuit. A parallel hardware accelerated fault simulator (PHAFS) has been proposed in order to reduce the complexity to O(L**2), where L is the number of levels of switches encountered when traversing from output to input. The paper presents the algorithm/complexity verification as needed for the prototyping of PHAFS. The verification includes a compiled code VHDL switch level fault simulator |
Year | DOI | Venue |
|---|---|---|
1993 | 10.1109/IWRSP.1993.263191 | Research Triangle Park, NC |
Keywords | Field | DocType |
CMOS integrated circuits,circuit analysis computing,computational complexity,digital integrated circuits,integrated circuit testing,parallel programming,specification languages,PHAFS,compiled code VHDL,computational complexity,fault simulation techniques,gate level faults,integrated circuits,parallel hardware accelerated fault simulator,switch level fault simulator | Stuck-at fault,Computer architecture,Computer science,Parallel computing,Real-time computing,Compiled language,CMOS,VHDL,Fault Simulator,Integrated circuit,Traverse,Computational complexity theory | Conference |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christopher A. Ryan | 1 | 4 | 1.43 |
| Joseph G. Tront | 2 | 42 | 4.95 |