Name
Abstract | ||
|---|---|---|
The authors propose a residue number system (RNS) architecture that realizes fast division. This architecture is fully developed in the particular case of eight-bit wordlength; in this case significant simplifications are reached. The whole divider appears as a combinatorial structure. A layout of the proposed architecture has been realized in a 1.5-μm CMOS technology, SPICE simulation of the circuit extracted from this layout has shown the overall propagation time in performing the division to be about 100 ns |
Year | DOI | Venue |
|---|---|---|
1989 | 10.1109/ICASSP.1989.266948 | Glasgow |
Keywords | DocType | ISSN |
cmos integrated circuits,computerised signal processing,digital signal processing chips,1.5 micron,100 ns,cmos technology,dsp chips,rns,spice simulation,architecture,combinatorial structure,digital signal processing,fast dividers,propagation time,residue number system,iterative methods,very large scale integration,arithmetic,adders | Conference | 1520-6149 |
Citations | PageRank | References |
1 | 0.64 | 1 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cadarilli, G.C. | 1 | 1 | 0.64 |
| Lojacono, R. | 2 | 2 | 1.00 |
| Salerno, M. | 3 | 1 | 0.64 |