Name
Abstract | ||
|---|---|---|
Many of the physical defects in CMOS circuits such as bridging and transistor stuck-on faults are not guaranteed to be detected by logic testing. In this paper, we examine the detection efficiency of stuck-at tests in covering all possible bridging faults in IDDQ environment. We generate stuck-at fault test vectors for combinational and sequential benchmark circuits using standard ATPG programs. The circuits are simulated with these vectors and power supply current was monitored for bridging faults. A high current state in a faulty circuit is considered as an indicator of fault detection. The test results are given in terms of intra-transistor and gate-level bridging fault coverage. Our results show that stuck-at test vectors can be used very efficiently for IDDQ testing of bridging faults, and extra effort to generate specialized test vectors may be unnecessary |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/ICVD.1994.282681 | VLSI Design |
Keywords | DocType | ISSN |
CMOS integrated circuits,circuit analysis computing,combinatorial circuits,integrated logic circuits,logic testing,sequential circuits,CMOS bridging faults,IDDQ detection,circuit simulation,combinational benchmark circuits,detection efficiency,gate-level bridging fault coverage,high current state,intra-transistor bridging fault coverage,physical defects,power supply current,sequential benchmark circuits,standard ATPG programs,stuck-at fault tests | Conference | 1063-9667 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hwang, S. | 1 | 0 | 0.34 |
| Rochit Rajsuman | 2 | 169 | 26.20 |
| Scott Davidson | 3 | 56 | 22.93 |