Name
Abstract | ||
|---|---|---|
Presents a novel switch level extension to parallel fault simulation and the switch level circuit partitioning needed for parallel processing. Using 9-valued logic, reverse level ordering and a parallel hardware accelerated fault simulator, simulation complexity is reduced to O(L**2), where L is the number of levels of switches encountered when traversing from output to input.<> |
Year | DOI | Venue |
|---|---|---|
1993 | 10.1109/VTEST.1993.313375 | Atlantic City, NJ, USA |
Keywords | Field | DocType |
CMOS integrated circuits,computational complexity,digital simulation,logic CAD,many-valued logics,parallel processing,hardware accelerated fault simulator,many-valued logic,parallel processing,parallel switch level fault simulation,reverse level ordering,switch level circuit partitioning | Stuck-at fault,Computer science,Parallel computing,CMOS,Real-time computing,Logic simulation,Acceleration,Fault Simulator,Crossover switch,Traverse,Computational complexity theory | Conference |
Citations | PageRank | References |
2 | 0.39 | 8 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christopher A. Ryan | 1 | 4 | 1.43 |
| Joseph G. Tront | 2 | 42 | 4.95 |