Title
Fast efficient simulation of write-buffer configurations
Abstract
Write-buffers have a significant impact on performance, especially in wide-issue superscalar systems with write-through caching. We develop fast efficient simulation methods for evaluating multiple write-buffer configurations together in a single-pass. Our results are also applicable for the simulation of other buffer structures. We first consider simulating non-coalescing write-buffers. We show that a particular buffer stalls only when smaller buffers do, and develop an algorithm where only the smallest buffer is explicitly simulated, and the stales of others are updated only as smaller buffers stall. Empirical performance comparisons show a speedup of up to 7.4 over simpler methods. We then extend this algorithm to simulate multiple coalescing write buffers, where we demonstrate up to a factor of 3.5 speedup. Finally, we demonstrate the impact that write-buffers have on CPI by presenting write-buffer simulation results on four SPEC benchmarks.<>
Year
DOI
Venue
1994
10.1109/HICSS.1994.323168
System Sciences, 1994. Proceedings of the Twenty-Seventh Hawaii International Conference  
Keywords
Field
DocType
buffer storage,digital simulation,parallel processing,performance evaluation,SPEC benchmarks,multiple coalescing write buffers,performance comparisons,simulation,superscalar systems,write-buffer configurations,write-through caching
Algorithm design,Computer science,Parallel processing,Parallel computing,Conference management,Write buffer,Superscalar,Spec#,Speedup
Conference
Volume
Citations 
PageRank 
1
0
0.34
References 
Authors
5
2
Name
Order
Citations
PageRank
Santosh G. Abraham1762124.08
Rabin A. Sugumar221168.51