Name
Abstract | ||
|---|---|---|
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and delay of the resulting system. Crossbar, Hierarchical Crossbar, and Mesh interconnection schemes have all been proposed for use in FPGA-based systems. In this paper we examine Mesh interconnection schemes, and propose several constructs for more efficient topologies. These reduce inter-chip delays by more than 60% over the basic 4-way Mesh. Introduction |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/92.711311 | VLSI) Systems, IEEE Transactions |
Keywords | Field | DocType |
multi-fpga systems,area,fixed arrays,design,delay,bipartite graph,software accelerators,network routing,mesh interconnection,trees (mathematics),mesh interconnection schemes,routing topology,logic arrays,network topology,delays,inter-chip delays,logic emulators,logic design,4-way mesh,mesh routing topologies,tree,mesh routing topology,graph theory,multi-fpga system,field programmable gate arrays,custom computing devices,mesh inter-connection schemes,gate array,emulation,microelectronics,chip,hardware,computer aided design,reconfigurable computing,indexing terms,topology,routing | Logic synthesis,Switched mesh,Computer science,Field-programmable gate array,Electronic engineering,Network topology,Wireless mesh network,Interconnection,Crossbar switch,Embedded system,Reconfigurable computing | Conference |
Volume | Issue | ISSN |
6 | 3 | 1063-8210 |
ISBN | Citations | PageRank |
0-8186-6565-3 | 20 | 2.19 |
References | Authors | |
12 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Scott Hauck | 1 | 2539 | 232.71 |
| Gaetano Borriello | 2 | 6050 | 777.11 |
| Carl Ebeling | 3 | 1405 | 185.32 |