Name
Title | ||
|---|---|---|
Generation and verification of timing constraints for fine-grain pipelined asynchronous data-path circuits |
Abstract | ||
|---|---|---|
Timing analysis is a method for verification of timing constraints in a digital circuit. Asynchronous circuits bring new concerns for timing analysis with their local completion circuits, which generate cycles in the circuit and require special handling. In this paper, constraints in fine-grain pipelined asynchronous data-path circuits are examined in detail and a tool environment for automatic generation and verification of these constraints are presented along with some sample layout results. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ASYNC.2002.1000301 | ASYNC |
Keywords | Field | DocType |
asynchronous circuits,circuit analysis computing,formal verification,logic CAD,pipeline processing,timing,asynchronous data-path circuits,automatic generation,automatic verification,completion detection,design methodology,digital circuit timing,fine-grain pipelined data-path circuits,local completion circuits,scalable delay insensitive model,timing analysis,timing constraints verification,tool environment | Signal processing,Asynchronous communication,Digital electronics,Computer science,Signal generator,Electronic engineering,Static timing analysis,Electronic circuit,Computer hardware,Formal verification,Encoding (memory) | Conference |
ISSN | ISBN | Citations |
1522-8681 | 0-7695-1540-1 | 1 |
PageRank | References | Authors |
0.41 | 3 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Metehan Özcan | 1 | 1 | 0.41 |
| Masashi Imai | 2 | 26 | 3.38 |
| Takashi Nanya | 3 | 200 | 35.46 |