Name
Abstract | ||
|---|---|---|
Today the most often applied DFT-strategy is full scan path. To reduce its overhead a partial scan path can be selected. For minimizing the size of the partial scan path existing testpatterns are used which will detect a part of the faults. Only the remaining faults, so called target faults, have to be addressed using partial scan. Different methods are given to adapt a partial scan path to the target faults. They do not depend on ATPG and therefore have very short runtimes. Results on sequential ATPG-benchmarks show that a strong reduction in the size of the partial scan path is possible. Also the combination of the structural selection and the selection with respect to target faults is proposed. First results prove its effectiveness.<> |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1109/VTEST.1991.208124 | Atlantic City, NJ, USA |
Keywords | Field | DocType |
VLSI,automatic testing,fault location,integrated circuit testing,DFT-strategy,minimized partial scan path,sequential ATPG-benchmarks,structural selection,target faults | Design for testing,Automatic test pattern generation,Partial scan,Algorithm design,Computer science,Fault detection and isolation,Scan chain,Real-time computing,Feedback loop,Electronic engineering,Very-large-scale integration | Conference |
Citations | PageRank | References |
2 | 0.40 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| H. H. S. Gundlach | 1 | 15 | 3.01 |
| Bernd K. Koch | 2 | 2 | 0.40 |
| Muller-Glaser, K.D. | 3 | 39 | 15.07 |