Name
Abstract | ||
|---|---|---|
RESPIN++ is a deterministic embedded test method tai- lored to system chips, which implement scan test at core level. The scan chains of one core of the system-on-a-chip are reused to decompress the patterns for another core. To implement the RESPIN++ test architecture only a few gates need to be added to the test wrapper. This will not affect the critical paths of the system. The RESPIN++ method re- duces both test data volume and test application time up to one order of magnitude per core compared to storing com- pacted test patterns on the ATE. If several cores may be tested concurrently, test data volume and test application time for the complete system test may be reduced even fur- ther. This paper presents the RESPIN++ test architecture and a compression algorithm for the architecture. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ETW.2002.1029637 | ETW |
Keywords | DocType | ISSN |
automatic testing,encoding,integrated circuit testing,logic testing,system-on-chip,RESPIN++ test architecture,core level scan test,deterministic embedded test method,encoding algorithm,system chip testing,system-on-a-chip,test application time reduction,test data volume reduction,test pattern compaction,test wrapper | Conference | 1530-1877 |
ISBN | Citations | PageRank |
0-7695-1715-3 | 31 | 1.29 |
References | Authors | |
19 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lars Schäfer | 1 | 31 | 1.29 |
| Rainer Dorsch | 2 | 135 | 12.60 |
| Hans-Joachim Wunderlich | 3 | 1822 | 155.30 |