Name
Abstract | ||
|---|---|---|
This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from Differential Cascode Voltage Switch Logic are compared with a checker that is composed of a tree of dual-rail (morphic) comparators to detect errors and signal completion. An efficient implementation is shown that compares favorably in speed and area with conventional completion signal generators. A simple pipeline is examined with error checkers at each computation stage and hand-shaking control circuits that are modified to improve error detection. Its error-detecting properties are discussed, and preliminary error simulation results are presented. Based on these studies we have concluded that self-timed logic offers considerable fault-tolerance potential due to its built-in redundancy that can be effectively exploited for error checking.<> |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/FTCS.1994.315653 | Austin, TX, USA |
Keywords | Field | DocType |
VLSI,circuit reliability,error detection,integrated circuit testing,logic testing,built-in redundancy,concurrent error detection,differential cascode voltage switch logic,dual-rail comparators,error checkers,error detection,error simulation,error-detecting properties,fault-tolerance potential,hand-shaking control circuits,pipeline,self-timed VLSI,self-timed logic,signal pairs | Comparator,Cascode,Computer science,Signal generator,Electronic engineering,Error detection and correction,Redundancy (engineering),Logic family,Electronic circuit,Very-large-scale integration,Computer engineering | Conference |
ISBN | Citations | PageRank |
0-8186-5520-8 | 10 | 1.37 |
References | Authors | |
8 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| David A. Rennels | 1 | 10 | 1.37 |
| Hyeong-Il Kim | 2 | 74 | 11.46 |