Name
Abstract | ||
|---|---|---|
The space-time mapping of the dependency matrix of an algorithm may be used to study proposed systolic array implementations. In this paper we consider nested loop structures and use the space-time mapping approach to examine six objective functions, processor pipelining rate, computation time, throughput, number of processing elements, geometric area and space utilization. An elementary expression for each of these objective functions is derived which depends only on the space-time transformation and the size of loops. Moreover, several necessary and sufficient conditions for optimizing an individual objective function are provided.<> |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/92.311644 | VLSI) Systems, IEEE Transactions |
Keywords | Field | DocType |
VLSI,logic CAD,matrix algebra,parallel algorithms,pipeline processing,systolic arrays,computation time,dependency matrix,geometric area,nested loop structures,objective functions,processing elements number,processor pipelining rate,space utilization,space-time mapping,systolic array designs,throughput | Pipeline (computing),Algorithm design,Computer science,Parallel algorithm,Systolic array,Real-time computing,Electronic engineering,Redundancy (engineering),Concurrent computing,Design structure matrix,Nested loop join | Journal |
Volume | Issue | ISSN |
2 | 3 | 1063-8210 |
Citations | PageRank | References |
5 | 0.67 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| C. N. Zhang | 1 | 28 | 6.89 |
| J. H. Weston | 2 | 6 | 1.39 |
| Yan, Y.-F. | 3 | 5 | 0.67 |